A Review: Hardware Implementation of AES Using Minimal Resources on FPGA

被引：0

作者：

Dhede, Onkar S. ^{[1
]}

Shah, S. K. ^{[1
]}

机构：

[1] STESs Smt Kashibai Navale Coll Engn, Dept Elect & Telecommun Engn, Sr 44-1,Off Sinhgad Rd, Pune 411041, Maharashtra, India

来源：

2015 INTERNATIONAL CONFERENCE ON PERVASIVE COMPUTING (ICPC) | 2015年

关键词：

AES (Advance Encryption Standard); Backend design; Field Programable Gate Array (FPGA); Frontend design; LUT's; Troughput;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Data protection in mobile as well as in computer networks is increasing day by day forcing developer to design the cryptographic algorithms. Also sending data securely over a transmission link is important in many applications. To solve this security issue the U.S. government adopted an algorithm Advanced Encryption Standard (AES) and is now used worldwide. As there is possibility that this algorithm may get hacked, hence this Paper presents the hardware for AES algorithm which can be implemented on Xilinx FPGA. The approach used to implement the AES algorithm is the use of Look Up Tables (LUTs). This approach will give the throughput between 3Gbps to 4Gbps with minimum utilization of resources on FPGA. Results can be verified using appropriate CAD tools.

引用

页数：3

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