DC offset control with application in a zero-IF 0.18 μm CMOS Bluetooth receiver chain

被引：3
|
作者：
Sanchez-Rodriguez, T. [2 ]
Galan, J. [1 ]
Carvajal, R. G. [2 ]
Lopez-Martin, A. [3 ]
Ramirez-Angulo, J. [4 ]
机构：
[1] Univ Huelva, Dept Ingn Elect Sistemas Informat & Automat, Huelva 21071, Spain
[2] Univ Seville, Dept Ingn Elect, Escuela Super Ingn, Seville 41092, Spain
[3] Univ Publ Navarra, Dept Ingn Elect & Elect, Pamplona 31006, Spain
[4] New Mexico State Univ, Klipsch Sch Elect Engn, Las Cruces, NM 88003 USA
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2010年 / 65卷 / 01期
关键词：
Direct-conversion receivers; DC offset; Low power and low-voltage circuits; QFG transistors; COMPENSATION;
D O I：
10.1007/s10470-009-9450-3
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A compact DC offset correction circuit based on the intrinsic properties of quasi-floating gate (QFG) transistors is presented. The proposed scheme uses a tuning mechanism to make its initial response faster improving the traditional large settling time of these circuits. A zero-IF baseband receiver chain suitable for Bluetooth that includes the proposed dc offset correction has been designed in a 0.18 mu m CMOS technology at 1.2 V supply voltage.
引用
收藏
页码：15 / 20
页数：6
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