Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

被引：0

作者：

Versen, Martin ^{[1
]}

Diaconescu, Dorina ^{[2
]}

Touzel, Jerome ^{[2
]}

机构：

[1] Qimonda AG, Campeon 1-12, D-85579 Neubiberg, Germany

[2] Infineon AG, D-81739 Munich, Germany

来源：

ISTFA 2007 | 2007年

关键词：

D O I：

暂无

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

引用

页码：252 / +

页数：2

共 50 条

[1] Tutorial on DRAM fault modeling and test pattern design
Cockburn, BF
[J]. 1998 INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING - PROCEEDINGS, 1998, : 66 - 66
[2] FAULT MODELING OF ECL DEVICES
MENON, SM
JAYASUMANA, AP
MALAIYA, YK
[J]. ELECTRONICS LETTERS, 1990, 26 (15) : 1105 - 1108
[3] Fault modeling and pattern-sensitivity testing for a multilevel DRAM
Redeker, M
Cockburn, BF
Elliott, DG
Xiang, YN
Ung, SA
[J]. PROCEEDING OF THE 2002 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, 2002, : 117 - 122
[4] Memory fault modeling trends: A case study
Hamdioui, S
Wadsworth, R
Reyes, JD
Van de Goor, AJ
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2004, 20 (03): : 245 - 255
[5] Memory Fault Modeling Trends: A Case Study
Said Hamdioui
Rob Wadsworth
John Delos Reyes
Ad J. van de Goor
[J]. Journal of Electronic Testing, 2004, 20 : 245 - 255
[6] An Industrial Case Study of Analog Fault Modeling
Yilmaz, Ender
Meixner, Anne
Ozev, Sule
[J]. 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 178 - 183
[7] Modeling and simulation of high redundancy actuator for fault-tolerance
Manohar, G. Arun
Vasu, V.
Srikanth, K.
[J]. MATERIALS TODAY-PROCEEDINGS, 2018, 5 (09) : 18867 - 18873
[8] Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices
Patel, Minesh
Kim, Jeremie S.
Hassan, Hasan
Mutlu, Onur
[J]. 2019 49TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS (DSN 2019), 2019, : 13 - 25
[9] A case study: Performance evaluation of a DRAM-based solid state disk
Oi, Hitoshi
[J]. 2007 JAPAN-CHINA JOINT WORKSHOP ON FRONTIER OF COMPUTER SCIENCE AND TECHNOLOGY, PROCEEDINGS, 2007, : 57 - 60
[10] Redundancy Evaluation Process of Processor Components for Permanent Fault Compensation
Koal, T.
Vierhaus, H. T.
[J]. 2015 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS), 2015,

← 1 2 3 4 5 →