A new formulation of fast diminished-one multioperand modulo 2n+1 adder

被引:0
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作者
Cao, B [1 ]
Chang, CH [1 ]
Srikanthan, T [1 ]
机构
[1] Nanyang Technol Univ, Ctr High Performance Embedded Syst, Singapore 637553, Singapore
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we introduce a new concept of composite carry-save adders with complementary end-around carry (CCSA with CEAC) to model multioperand modulo 2(n)+1 adder. The CCSA with CEAC is a combination of CSA with EAC and a constant residue counter, where the latter is used to account for the intrinsic residues generated by the diminished-one modulo 2(n)+1 additions at various levels of the multioperand modulo adder (MOMA). With the proposed reduction rules, we prove that the companion residue counter tree can be eliminated. The resultant architecture is a universal structure for the diminished-one multioperand modulo 2(n)+1 adder, consisting of only a CSA with CEAC tree and a 2-input diminished-one adder. The latter can be implemented by any of the efficient solutions reported in the literature, which make the proposed structure operates as fast as the high-speed modulo 2(n)-1 MOMA.
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页码:656 / 659
页数:4
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