A hardware packet Re-Sequencer Unit for Network Processors

被引：0

作者：

Meitinger, Michael ^{[1
]}

Ohlendorf, Rainer ^{[1
]}

Wild, Thomas ^{[1
]}

Herkersdorf, Andreas ^{[1
]}

机构：

[1] Tech Univ Munich, D-80290 Munich, Germany

来源：

ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2008, PROCEEDINGS | 2008年 / 4934卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Network Processors (NP) usually are designed as multi-processor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed.

引用

页码：85 / 97

页数：13

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