Electromigration Modeling and Full-chip Reliability Analysis for BEOL Interconnect in TSV-based 3D ICs

Electromigration (EM) is a critical problem for interconnect reliability of modern integrated circuits (ICs), especially as the feature size becomes smaller. In three-dimensional (3D) IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through silicon vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to the TSV can also cause reduction in the failure time of wires. However, there is very little study on EM issues that consider TSVs in 3D ICs. In this paper, we show the impact of TSV stress on EM failure time of metal wires in 3D ICs. We model the impact of TSV on stress variation in wires. We then perform detailed modeling of the impact of stress on EM failure time of metal wires. Based on our analysis, we build a detailed library to predict the failure time of a given wire based on current density, temperature and stress. We then propose a method to perform fast full-chip simulation, to determine the various EM related hot-spots in the design. We also propose a simple routing-blockage scheme to reduce the EM related failures near the TSVs, and see its impact on various metrics.