Real-time target detection architecture based on reduced complexity hyperspectral processing

This paper presents a real-time target detection architecture for hyperspectral image processing. The architecture is based on a reduced complexity algorithm for high-throughput applications. We propose an efficient pipelined processing element architecture and a scalable multiple-processing element architecture by exploiting data partitioning. We present a processing unit modeling based on the data reduction algorithm in hyperspectral image processing and propose computing structure, that is, to optimize memory usage and eliminates memory bottleneck. We investigate the interconnection topology for the multiple processing element architecture to improve the speed. The proposed architecture is designed and implemented in FPGA to illustrate the relationship between hardware complexity and execution throughput of hyperspectral image processing for target detection. Copyright (C) 2008 Kyoung-Su Park et al.