Efficient Custom Instruction Enumeration for Extensible Processors

被引:0
|
作者
Xiao, Chenglong [1 ]
Casseau, Emmanuel [1 ]
机构
[1] Univ Rennes 1, Irisa, INRIA, Rennes, France
关键词
Extensible processors; ASIPs; DFG; custom instruction; custom instruction generation algorithm;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically custom instructions from a high-level application code. In this paper, we propose an efficient and flexible algorithm for the exact enumeration of custom instructions. The algorithm can be tuned to generate all possible patterns or only connected patterns. Compared to a previously proposed well-known algorithm, our algorithm can achieve orders of magnitude speedup.
引用
收藏
页码:211 / 214
页数:4
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