Providing Accountability in Heterogeneous Systems-on-Chip

被引:1
|
作者
Kalayappan, Rajshekar [1 ,2 ]
Sarangi, Smruti R. [2 ]
机构
[1] Indian Inst Technol Dharwad, Dharwad 580011, Karnataka, India
[2] Indian Inst Technol Delhi, New Delhi 110016, India
关键词
Accountability; auditing; SoC; third-party IPs; accelerators; heterogeneous processors;
D O I
10.1145/3241048
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
When modern systems-on-chip (SoCs), containing designs from different organizations, miscompute or underperform in the field, discerning the responsible component is a non-trivial task. A perfectly accountable system is one in which the on-chip component at fault is always unambiguously detected. The achievement of accountability can be greatly aided by the collection of runtime information that captures the events in the system that led to the error. Such information collection must be fair and impartial to all parties. In this article, we prove that logging messages communicated between components from different organizations is sufficient to provide accountability, provided the logs are authentic. We then construct a solution based on this premise, with an on-chip trusted auditing system to authenticate the logs. We present a thorough design of the auditing system, and demonstrate that its performance overhead is a mere 0.49%, and its area overhead is a mere 0.194% (in a heterogeneous 48 core, 400mm 2 chip). We also demonstrate the viability of this solution using three representative bugs found in popular commercial SoCs.
引用
收藏
页数:24
相关论文
共 50 条
  • [1] A Formal Approach to Accountability in Heterogeneous Systems-on-Chip
    Kalayappan, Rajshekar
    Sarangi, Smruti R.
    IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2021, 18 (06) : 2926 - 2940
  • [2] Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip
    Spagnolo, Fanny
    Perri, Stefania
    Frustaci, Fabio
    Corsonello, Pasquale
    2020 9TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2020, : 289 - 293
  • [3] Stereo vision architecture for heterogeneous systems-on-chip
    Stefania Perri
    Fabio Frustaci
    Fanny Spagnolo
    Pasquale Corsonello
    Journal of Real-Time Image Processing, 2020, 17 : 393 - 415
  • [4] MRAPI implementation for Heterogeneous Reconfigurable Systems-on-Chip
    Gantel, L.
    Benkhelifa, M. E. A.
    Verdier, F.
    Lemonnier, F.
    2014 IEEE 22ND ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2014), 2014, : 239 - 239
  • [5] Stereo vision architecture for heterogeneous systems-on-chip
    Perri, Stefania
    Frustaci, Fabio
    Spagnolo, Fanny
    Corsonello, Pasquale
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2020, 17 (02) : 393 - 415
  • [6] Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip
    Perri, Stefania
    Sestito, Cristian
    Spagnolo, Fanny
    Corsonello, Pasquale
    JOURNAL OF IMAGING, 2020, 6 (09)
  • [7] Designing efficient irregular networks for heterogeneous systems-on-chip
    Neeb, Cristian
    Wehn, Norbert
    JOURNAL OF SYSTEMS ARCHITECTURE, 2008, 54 (3-4) : 384 - 396
  • [8] Designing efficient irregular networks for heterogeneous systems-on-chip
    Neeb, Christian
    Wehn, Norbert
    DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2006, : 665 - +
  • [9] Reliability Evaluation of Heterogeneous Systems-on-Chip for Automotive ECUs
    Azimi, Sarah
    Moramarco, Annarita
    Sterpone, Luca
    2017 IEEE 26TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE), 2017, : 1291 - 1296
  • [10] A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip
    Perri, Stefania
    Spagnolo, Fanny
    Corsonello, Pasquale
    ELECTRONICS, 2020, 9 (02)