Multi-Core for K-Means Clustering on FPGA

被引：22

作者：

Canilho, Jose ^{[1
]}

Vestias, Mario ^{[2
]}

Neto, Horacio ^{[1
]}

机构：

[1] Univ Lisbon, Inst Super Tecn, INESC ID, P-1699 Lisbon, Portugal

[2] Inst Politecn Lisboa, ISEL, INESC ID, Lisbon, Portugal

来源：

2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL) | 2016年

关键词：

Clustering; K-means; Hardware/Software Co-design; Hardware Acceleration; Systems on Chip;

D O I：

10.1109/FPL.2016.7577313

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

In this paper, a configurable many-core hardware/software architecture is proposed to efficiently execute the widely known and commonly used K-means clustering algorithm. A prototype was designed and implemented on a Xilinx Zynq-7000 All Programmable SoC. A single core configured with the slowest configuration achieves a 10X speed-up compared to the software only solution. The system is fully scalable and capable of achieving much higher speed-ups by increasing its parallelism.

引用

页数：4

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