Asymptotic upper bound for multiplier design

被引：7
|
作者：
Pinch, RGE
机构：
[1] University of Cambridge, Dept. of Pure Math. and Math. Stat., Cambridge CB2 1SB
来源：
ELECTRONICS LETTERS | 1996年 / 32卷 / 05期
关键词：
multiplying circuits; digital circuits;
D O I：
10.1049/el:19960348
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The cost, in terms of adders/subtractors, of multiplication by n-bit integers when shifts are free is shown to be of the order of n/(log n)(alpha) for any alpha < 1.
引用
收藏
页码：420 / 421
页数：2
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