Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine: Application to Wireless Heart-Rate Monitoring

被引：0
|
作者：
El-Sayed, Mohammad [1 ]
Koch, Peter [1 ]
Le Moullec, Yannick [2 ]
机构：
[1] Aalborg Univ, Dept Elect Syst, Aalborg, Denmark
[2] Tallinn Univ Technol, TJ Seebeck Dept Elect, Tallinn, Estonia
来源：
2015 NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP & INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC) | 2015年
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D O I：
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.
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页数：5
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