An effective output-oriented algorithm for low power multipartition architecture

Circuit partition for low power is one of the useful techniques which reduce power dissipation by confining the switching activity to a subcircuit. In this paper, we propose an effective output-oriented partition algorithm for low power combinational logic circuit. Unlike previous study, we discuss the relationship among power dissipation, area complexity and input/output behavior of a combinational logic circuit rather than inspect its logic function. Experimental results show that our algorithm can obtain sizable power saving over a wide range of MCNC benchmarks.