Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs

被引：13
|
作者：
Chung, Chia-Che [1 ]
Ye, Hung-Yu [1 ]
Lin, H. H. [2 ]
Wan, W. K. [2 ]
Yang, M. -T. [2 ]
Liu, C. W. [3 ,4 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
[2] MediaTek Inc, Hsinchu 300, Taiwan
[3] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan
[4] Natl Taiwan Univ, Grad Inst Photon & Optoelect, Taipei 106, Taiwan
来源：
IEEE ELECTRON DEVICE LETTERS | 2019年 / 40卷 / 12期
关键词：
Vertically stacked nanosheets; gate-all-around (GAA) MOSFETs; self-heating; threshold voltage (V-t); FINFET; VARIABILITY;
D O I：
10.1109/LED.2019.2945474
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The V-t difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher V-t difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The V-t difference increases with the increasing channel number and nanosheet width.
引用
收藏
页码：1913 / 1916
页数：4
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