Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

被引：5
|
作者：
Kerber, A. [1 ]
机构：
[1] GLOBALFOUNDRIES Inc, Reliabil Engn, 400 Stone Break Rd Extens, Malta, NY 12020 USA
来源：
MICROELECTRONICS RELIABILITY | 2016年 / 64卷
关键词：
High-k dielectrics; Metal gate; BTI; TDDB; RTN; SRAM; Ring-oscillators; CMOS; DEGRADATION; METHODOLOGY; STRESS;
D O I：
10.1016/j.microrel.2016.07.071
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on. (C) 2016 Published by Elsevier Ltd.
引用
收藏
页码：145 / 151
页数：7
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