Effect of Oxidation-Induced Tensile Strain on Gate-All-Around Silicon-Nanowire-Based Single-Electron Transistor Fabricated Using Deep-UV Lithography

We report on the electrical characteristics of gate-allaround silicon nanowires (SiNWs) based single-electron transistors (SETs) operating at room temperature. The SiNWs, fabricated using CMOS compatible conventional KrF lithography, have a diameter of around 3 nmand different lengths ranging from 200 to 500 nm. Coulomb blockade oscillations are found to be dependent on the length of the SiNWs, more prominent for longer than shorter SiNWs. For the shortest device of 200 nm, no oscillation is seen and the I-D - V-G curve reverts to that of a typical MOSFET. The results are interpreted in terms of the effect of SiNW length on the oxidation-induced tensile strain, and consequently, the tunneling barrier height developed in the wires. The study reveals that the SiNW length is a crucial parameter in the design of SiNW-based SETs.