Hardware/software co-verification platform for EOS design

被引:0
|
作者
Wang, P [1 ]
Liu, JS [1 ]
Zeng, LG [1 ]
机构
[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
关键词
hardware/software co-verification; EOS;
D O I
10.1109/ICASIC.2003.1277522
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Ethernet over SDH/SONET (EOS) has become a hotspot in data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However. implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs. controlling programs for the microprocessor and a console program with GUT (Graphical User lnterface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed in verifying several IP (Intellectual Property) blocks of our EOS chip. Moreover. it is flexible and can be applied as a general-purpose verification platform.
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收藏
页码:195 / 198
页数:4
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