NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-Core Systems

In a multi-core environment with several applications executing in parallel, system performance is significantly impacted by network and memory performance. The manner in which network packets and off-chip memory bound packets are handled determines end-to-end latencies across the network and memory. Several techniques have been proposed in the past that schedule packets in an application-aware manner or memory requests in a DRAM row/bank locality aware manner. In this paper, we propose a holistic framework that integrates novel scheduling techniques for both network and memory accesses and operates cohesively in an application-aware and memory-aware manner to optimize overall system performance. Experimental results indicate that our technique performs well for systems with high speed memories, improving system throughput by up to 16.7%, memory latency by up to 11%, and energy consumption by up to 10% compared to prior work on NoC packet scheduling.