Analysis and optimization of ground bounce in digital CMOS circuits

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the buffer propagation delay and the optimum taper factor is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of the on-chip decoupling capacitor on ground bounce waveform and the circuit performance is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.