A current-mode filter for wireless systems in 65 nm CMOS technology

被引：0

作者：

Uhrmann, H. ^{[1
]}

Zimmermann, H. ^{[1
]}

机构：

[1] Vienna Univ Technol, Inst Elect Measurements & Circuit Design, A-1040 Vienna, Austria

来源：

MIXDES 2008: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2008年

关键词：

current-mode; low-pass; Butterworth; integrator; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3rd-order current-mode Butterworth low-pass filter is proposed, which is based on current-mode integrators. A new current-mode integrator is realized that offers an area-saving chip design. The low-pass filter is designed and realized in 65nm. low-power CMOS technology and needs 215 mu m x 221 mu m chip area. The power consumption is 12 mW at a supply voltage of 1.2 V. The cut-off frequency of the filter is switchable between I MHz and 4 MHz. The measurement of noise and total harmonic distortion result in a dynamic range of 77.3 dB and 71.3 dB for 1 MHz and 4 MHz, respectively. The filter is designed to be part of a transmit path in a Software Defined Radio (SDR) system on chip that fits for a couple of wireless applications.

引用

页码：165 / 168

页数：4

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