High Quality IP Design using High-Level Synthesis Design Flow

In this paper we will describe practical experiences about the use of high-level synthesis technologies to achieve higher performance, higher quality, and lower power for IP designs as compared to traditional RTL design. We will demonstrate how the introduction of three key techniques, interface-based design, architectural exploration and congestion-aware high-level synthesis, were utilized to achieve higher quality IP designs. In real application results, we will show significantly better QoR (Quality-of-Results) using high-level synthesis than the traditional RTL design flow by utilizing the above three key technologies.