A high-speed FFT processor for OFDM systems

被引：0

作者：

Son, BS ^{[1
]}

Jo, BG ^{[1
]}

Sunwoo, MH ^{[1
]}

Kim, YS ^{[1
]}

机构：

[1] Ajou Univ, Sch Elect & Comp Engn, Paldal Ku, Suwon 442749, South Korea

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a singic-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed using the Samsung(TM) 0.5mum SOG cell library (KG80). the implemented FFT processor consists of 98,326 gates excluding RAM. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6mus.

引用

页码：281 / 284

页数：4

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