A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS

This paper describes a digital-mapping direct digital frequency synthesizer having a tuning and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic microwave-integrated circuit (MMIC) is the first solution supporting a sampling rate of 7 GS/s with frequency modulation, phase modulation (PM), and amplitude modulation (AM) in the digital domain. It includes a 14 bits pipelined ripple-carry phase adder and a 10-bits high-speed amplitude multiplier. The minimum frequency, phase, and amplitude steps are 417.2 Hz, 0.022 degrees, and 1.17 mV, respectively. A proof-of-concept chip with an active area of 0.23 mm(2) was fabricated in a 1P9M 65-nm CMOS process and characterized in low-profile quad flat package (LQFP). The worst case wideband/narrowband spurious-free dynamic range is 32/42 dBc. This system consumes 85.9 mW/(GS/s) from a 1.2-V power supply when the PM/AM are enabled, resulting in an figure of merit (FoM) of 469.6 GS/s.2((SFDR/6))/W. The absolute single sideband phase noise at 100 KHz offset from the carrier was better than -125 dBc/Hz in all the evaluated frequencies. A latency of 12.86 ns was measured when operating at 7 GS/s.