Improving source/drain contact resistance of amorphous indium-gallium-zinc-oxide thin-film transistors using an n+-ZnO buffer layer

被引:9
|
作者
Hung, Chien-Hsiung [1 ]
Wang, Shui-Jinn [1 ,2 ]
Lin, Chieh [1 ]
Wu, Chien-Hung [3 ]
Chen, Yen-Han [1 ]
Liu, Pang-Yi [1 ]
Tu, Yung-Chun [1 ]
Lin, Tseng-Hsing [1 ]
机构
[1] Natl Cheng Kung Univ, Inst Microelect, Dept Elect Engn, Tainan 701, Taiwan
[2] Natl Cheng Kung Univ, Adv Optoelect Technol Ctr, Tainan 701, Taiwan
[3] Chung Hua Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
ROOM-TEMPERATURE; GLASS; PERFORMANCE; DEPOSITION; PRESSURE; DAMAGE; N-2;
D O I
10.7567/JJAP.55.06GG05
中图分类号
O59 [应用物理学];
学科分类号
摘要
To avoid high temperature annealing in improving the source/drain (S/D) resistance (RDS) of amorphous indium-gallium-zinc-oxide (alpha-IGZO) thinfilm transistors (TFTs) for flexible electronics, a simple and efficient technique using a sputtering-deposited n(+)-ZnO buffer layer (BL) sandwiched between the S/D electrode and the alpha-IGZO channel is proposed and demonstrated. It shows that the RDS of alpha-IGZO TFTs with the proposed n(+)-ZnO BL is reduced to 8.1 x 10(3)Omega as compared with 6.1 x 10(4)Omega of the conventional one. The facilitation of carrier tunneling between the S/D electrode and the alpha-IGZO channel through the use of the n(+)-ZnO BL to lower the effective barrier height therein is responsible for the RDS reduction. Effects of the chamber pressure on the carrier concentration of the sputtering-deposited n(+)-ZnO BL and the thickness of the BL on the degree of improvement in the performance of alpha-IGZO TFTs are analyzed and discussed. (C) 2016 The Japan Society of Applied Physics
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页数:6
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