Reliability and Scalability of FinFET Split-Gate MONOS Array with Tight Vth Distribution for 16/14nm-node Embedded Flash

被引：0

作者：

Tsuda, S. ^{[1
]}

Saito, T. ^{[1
]}

Nagase, H. ^{[1
]}

Kawashima, Y. ^{[1
]}

Yoshitomi, A. ^{[1
]}

Okanishi, S. ^{[1
]}

Hayashi, T. ^{[1
]}

Maruyama, T. ^{[1
]}

Inoue, M. ^{[1
]}

Muranaka, S. ^{[1
]}

Kato, S. ^{[1
]}

Hagiwara, T. ^{[1
]}

Saito, H. ^{[1
]}

Yamaguchi, T. ^{[1
]}

Kadoshima, M. ^{[1
]}

Maruyama, T. ^{[1
]}

Mihara, T. ^{[1
]}

Yanagita, H. ^{[1
]}

Sonoda, K. ^{[1
]}

Yamashita, T. ^{[1
]}

Yamaguchi, Y. ^{[1
]}

机构：

[1] Renesas Elect Corp, Tokyo, Japan

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.

引用

页数：4

共 5 条

[1] First Demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond
Tsuda, S.
Kawashima, Y.
Sonoda, K.
Yoshitomi, A.
Mihara, T.
Narumi, S.
Inoue, M.
Muranaka, S.
Maruyama, T.
Yamashita, T.
Yamaguchi, Y.
Hisamoto, D.
2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
[2] Investigation of the Data Retention Mechanism and Modeling for the High Reliability Embedded Split-Gate MONOS Flash Memory
Kawashima, Yoshiyuki
Hashimoto, Takashi
Yamakawa, Ichiro
2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2015,
[3] A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability
Do, Nhan
Tee, Latt
Hariharan, Santosh
Lemke, Steven
Tadayoni, Mandana
Yang, Will
Wu, M. T.
Kim, Jinho
Chen, Yueh-Hsin
Su, Chien-Sheng
Tiwari, Vipin
Zhou, Stephen
Qian, Rodger
Yue, Ian
2015 IEEE 7TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2015, : 46 - 48
[4] 40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 °C
Kono, Takashi
Ito, Takashi
Tsuruda, Tamaki
Nishiyama, Takayuki
Nagasawa, Tsutomu
Ogawa, Tomoya
Kawashima, Yoshiyuki
Hidaka, Hideto
Yamauchi, Tadaaki
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (01) : 154 - 166
[5] A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C
Taito, Yasuhiko
Kono, Takashi
Nakano, Masaya
Saito, Tomoya
Ito, Takashi
Noguchi, Kenji
Hidaka, Hideto
Yamauchi, Tadaaki
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (01) : 213 - 221

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