Delay Variation Compensation through Error Correction using Razor

被引：0

作者：

Chua, Adelson N. ^{[1
]}

Maestro, Rico Jossel M. ^{[1
]}

Alba, Mark Earvin V. ^{[1
]}

Lofamia, Wes Vernon V. ^{[1
]}

Pelayo, Bernard Raymond D. ^{[1
]}

Fabay, Ken Bryan F. ^{[1
]}

Jardin, John Cris F. ^{[1
]}

Jocson, Kervin John C. ^{[1
]}

Madamba, Joy Alinda R. ^{[1
]}

Hizon, John Richard E. ^{[1
]}

Alarcon, Louis P. ^{[1
]}

机构：

[1] Univ Philippines Diliman, Elect & Elect Engn Inst, Microelect & Microprocessors Lab, Quezon City, Philippines

来源：

PROCEEDINGS 2015 6TH INTERNATIONAL WORKSHOP ON CMOS VARIABILITY (VARI) | 2015年

关键词：

ARM9; PVT Delay variations; Error correction; Razor technique;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.

引用

页码：5 / 8

页数：4

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