An improved architecture for bit-level matrix multiplication

We present a novel bit-level architecture where each processing element does a simple operation of adding three to six bits to generate one partial sum bit and one to two carryout bits. We gain speedup over word-level because individual bits of a word do not have to be processed as a unit in a bit-level architecture. In [1], two bit-level architectures for fixed point matrix multiplication are proposed that are O(log p) times faster than the fastest word-level architecture where p is the word length. The architecture presented in this paper is even faster than the two in [1] by breaking the critical path in the dependence graph into half: We show basic ideas of how to gain speedup in our design, how to establish the dependence structure and how to derive the final design. We also show our design is time optimal for our dependence structure and has a speedup of 50% or more over the designs presented in [1]. We are implementing the design on a Xilinx FPGA chip, which shows a potential speedup over Xilinx multiplier macro. Our approach can be used to map algorithms to hardware.