A Partial Task Replication Algorithm for Fault-Tolerant FPGA-based Soft-Multiprocessors

FPGA-based multiprocessors, referred as soft-multiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks in multiple processors and comparing their output; 2) errors are corrected by re-downloading the fault-free bitstream; 3) errors are recovered from correct checkpoints. To evaluate the proposed method, a FPGA containing four and eight processors running randomly generated task graphs is evaluated. The simulation results show that the performance overhead of the proposed method for four and eight processors is 20% and 15%, respectively. These values for lockstep method are about 90% and 45%, respectively. Moreover, the area overhead of the proposed method is zero.