Memory power reduction for the high-speed implementation of turbo codes

Reliable data-transmission is a very important issue for wireless communication systems. Data-transmission with near-optimal bit error rates at low Signal to Noise Ratios (SNRS) can be achieved by applying turbo codes. However, the hardware implementation of a turbo decoder for high bit rates is challenging. This is partly due to the inherent decoding latency of the Maximum-A-Posteriori (MAP)algorithm, which is the key building block of the decoder. Moreover, power consumption in the MAP algorithm turns out to be a problem at high data rates. An analysis of power consumption in the MAP-algorithm has indicated a bottleneck in memory accesses. Therefore, the Data Transfer and Storage Exploration (DTSE) methodology, developed at IMEC, has been applied. This paper extensively describes some DTSE-optimizations for the MAP-algorithm in the context of the entire methodology. Applying the DTSE-methodology has allowed reaching the required data rates for wireless communications. Moreover, it has also resulted in reduced power consumption and lower latency.