A shared cache-aware Task scheduling strategy for multi-core systems

被引:1
|
作者
Tang, Xiaoyong [1 ]
Yang, Xiaopan [1 ]
Liao, Guiping [1 ]
Zhu, Xinghui [1 ]
机构
[1] Hunan Agr Univ, Informat Sci & Technol Coll, Southern Reg Collaborat Innovat Ctr Grain & Oil C, Changsha 410128, Hunan, Peoples R China
关键词
Cache; Multi-core; task scheduling; schedule length; average response time; PERFORMANCE; ALGORITHM; EFFICIENT; SCHEME; CPU;
D O I
10.3233/JIFS-169036
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In the past few years, multi-core processors incorporating four, six, eight, or more cores on a single die have become ubiquitous. Those cores, having their own private caches, often share a higher level cache memory, which leads to compete among different tasks. This can seriously affect the average performance of multi-core systems as the probability of cache hit could be lowered. In realizing this, we study the problem of scheduling bag-of-tasks (BoT) applications with shared cache constraint on multi-core systems. We first use cache space isolation techniques to divide shared caches into partitions. Then, we give a motivational example and outline the shared cache aware scheduling problem of multi-core systems. Finally, to provide an optimum solution for this problem, we propose a heuristic shared cache contention aware scheduling (SCAS) algorithm on multi-core systems. Our extensive simulation performance evaluation study clearly demonstrate that our proposed SCAS algorithm outperforms the existing traditional scheduling algorithm Min-min and the modified algorithm MSCAS in terms of schedule length and average response time.
引用
收藏
页码:1079 / 1088
页数:10
相关论文
共 50 条
  • [1] Shared Cache-aware Scheduling Algorithm on Multi-core Systems
    Tang, Xiao-Yong
    [J]. INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND COMMUNICATION ENGINEERING (CSCE 2015), 2015, : 1249 - 1255
  • [2] Cache-Aware Task Scheduling on Multi-Core Architecture
    Yang, Teng-Feng
    Lin, Chung-Hsiang
    Yang, Chia-Lin
    [J]. 2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 139 - 142
  • [3] Cache-Aware Virtual Machine Scheduling on Multi-Core Architecture
    Hong, Cheol-Ho
    Kim, Young-Pil
    Yoo, Seehwan
    Lee, Chi-Young
    Yoo, Chuck
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2012, E95D (10): : 2377 - 2392
  • [4] Work-in-Progress: Cache-Aware Partitioned EDF Scheduling for Multi-Core Real-Time Systems
    Guo, Zhishan
    Zhang, Ying
    Wang, Lingxiang
    Zhang, Zhenkai
    [J]. 2017 IEEE REAL-TIME SYSTEMS SYMPOSIUM (RTSS), 2017, : 384 - 386
  • [5] Performance Characterization and Cache-Aware Core Scheduling in a Virtualized Multi-Core Server under 10GbE
    Guo, Danhua
    Liao, Guangdeng
    Bhuyan, Laxmi N.
    [J]. PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, 2009, : 168 - 177
  • [6] CATS: cache-aware task scheduling for Hadoop-based systems
    Lim, Byungnam
    Kim, Jong Wook
    Chung, Yon Dohn
    [J]. CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS, 2017, 20 (04): : 3691 - 3705
  • [7] Cache-Aware Utilization Control for Energy Efficiency in Multi-Core Real-Time Systems
    Fu, Xing
    Kabir, Khairul
    Wang, Xiaorui
    [J]. PROCEEDINGS OF THE 23RD EUROMICRO CONFERENCE ON REAL-TIME SYSTEMS (ECRTS 2011), 2011, : 102 - 111
  • [8] CATS: cache-aware task scheduling for Hadoop-based systems
    Byungnam Lim
    Jong Wook Kim
    Yon Dohn Chung
    [J]. Cluster Computing, 2017, 20 : 3691 - 3705
  • [9] Cache-Aware Real-Time Virtualization for Clustered Multi-Core Platforms
    Lim, Yoojin
    Kim, Hyoseung
    [J]. IEEE ACCESS, 2019, 7 : 128628 - 128640
  • [10] Characterising the performance of cache-aware placement of Virtual Machines on a multi-core architecture
    Emeneker, Wesley
    Apon, Amy
    [J]. INTERNATIONAL JOURNAL OF AD HOC AND UBIQUITOUS COMPUTING, 2012, 10 (02) : 84 - 95