Enabling Partial Reconfiguration for Coprocessors in Mixed Criticality Multicore Systems Using PCI Express Single-Root I/O Virtualization

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.