Life Estimation of Analog IC Based on Accelerated Degradation Testing

被引：0

作者：

Luo, Jun ^{[1
]}

Qin, Guolin ^{[1
]}

Tan, Kaizhou ^{[1
]}

Zhao, Shenglei ^{[2
]}

Chen, Haoran ^{[2
]}

Hao, Yue ^{[2
]}

机构：

[1] CETC, Sichuan Inst Solid State Circuits, Dept Qual & Reliabil Assurance, Chongqing, Peoples R China

[2] Xidian Univ, Sch Microelect, Xian, Shaanxi, Peoples R China

来源：

PROCEEDINGS OF 2014 10TH INTERNATIONAL CONFERENCE ON RELIABILITY, MAINTAINABILITY AND SAFETY (ICRMS), VOLS I AND II | 2014年

关键词：

semiconductor analog ICs; accelerated degradation testing; reliability; life estimation;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

For high reliability semiconductor analog ICs, it is difficult to estimate their lifetime by using traditional reliability analysis methods since no enough failure data can be obtained in a relatively short period of time. Aiming at this problem, firstly, a general procedure for an accelerated degradation testing was proposed to analyze the lifetime of analog ICs under actual operating conditions according to the characteristics of their degradation behavior in this paper. Then, accelerated models and performance degradation models of analog ICs were introduced. Finally, the engineering practicability of the presented method is verified with a case of a certain type of voltage reference analog IC applied in certain aerospace electronic system.

引用

页码：817 / 821

页数：5

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