Sub-micron electrical interconnection enabled ultra-high I/O density wafer level SiP Integration

To improve the latency and bandwidth performance for future high performance computing application, a sub-micron electrical interconnection composed of metal capping layer with sub-micron thickness on typical copper CMP (chemical mechanical polish) BEOL (back-end of line) structure is demonstrated, and the corresponding metal deposition including Ni, Pd, Au using electro-less technique are reported in this study. In this structure, sub-micron size metal pads in the present copper BEOL technology are formed utilizing electroless deposition and significantly simplify the current litho-based "bumping" processes and is cost-effective in production. With this structure, I/O density is shown to be higher than 10(6)/cm(2), and the improvement in chip embedded passive device is achieved. Moreover, a polymer based material as the protection underfill was performed to evaluate the sub-micron gap filling feasibility. Besides, a wet chemical bond formation for chip stacking technology is proposed with a simple cost-effective joint structure (Cu pad-Metal-Cu pad) and an electroless deposition process with low processing temperature (<= 70 degrees C) was utilized. This study demonstrated the electroless bond formation, which consists of pre-aligned die stacking with adhesive spacers and subsequent wet chemical electroless plating process to form joints between top tier and bottom tier Cu pads.