Implementation of 85V high side LDMOS with n-layer in a 0.35um BCD process

被引：0

作者：

Ko, Choul-Joo ^{[1
]}

Lee, Sang-Yong ^{[1
]}

Park, Il-Yong ^{[1
]}

Park, Cho-Eung ^{[1
]}

Jun, Bon-Keun ^{[1
]}

Lee, Yong-Jun ^{[1
]}

Kang, Chan-Hee ^{[1
]}

Lee, Jae-O ^{[1
]}

Kim, Nam-Joo ^{[1
]}

Yoo, Kwang-Dong ^{[1
]}

机构：

[1] Dongbu Hitek, Puchon 420712, Gyeonggi Do, South Korea

来源：

ISPSD 08: PROCEEDINGS OF THE 20TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper report 85V high-side LDMOS which is implemented in a conventional 0.35um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80V SOI LDMOS.

引用

页码：103 / 106

页数：4

共 3 条

[1] Fundamentals of side isolation LDMOS device with 0.35um CMOS compatible process
Deivasigamani, R.
Sheu, Gene
Yang, Shao Ming
Sai, S. Krishna
Selvendran, S.
Aryadeep, Chirag
Chen, Po-An
2016 E-MANUFACTURING AND DESIGN COLLABORATION SYMPOSIUM (EMDC), 2016,
[2] A 150V Novel High-Voltage LDMOS in a 0.18um BCD Plug-In Process
Chen, Yen-Ming
Lee, Chiu-Ling
Tsai, Min-Hsuan
Lee, Chiu-Te
Wang, Chih-Chong
PRODCEEDINGS OF THE 2018 IEEE 30TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2018, : 331 - 334
[3] Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
Kumar, Ankit
Hapsari, Emita Yulia
Kumar, Vasanth
Mrinal, Aryadeep
Sheu, Gene
Yang, Shao-Ming
Ningaraju, Vivek
2013 IEEE 8TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2013, : 78 - 80

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