Design and modeling of a high-Q on-chip hairpin inductor for RFIC applications

被引：0
|
作者：
Ni, W [1 ]
Yuan, XJ [1 ]
Tretiakov, YV [1 ]
Groves, R [1 ]
Larson, LE [1 ]
机构：
[1] IBM Microelect, IBM La Jolla Foundry Applicat Ctr, San Diego, CA 92122 USA
来源：
2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2003年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design and modeling of a high Q hairpin inductor is presented. The inductor is designed and fabricated using the thick top-level metal (4um thickness, Mum away from the substrate) in an IBM 0.5um SiGe BiCMOS process to provide very high peak Q, approaching 27 from 2 to 4GHz, specifically for integrated voltage-controlled-oscillator (VCO) applications. A broadband lumped-element model is also developed for this structure. The modeling methodology is verified using commercial field solvers (IE3D and ADS Momentum) and hardware measured data, the results show that the derived model is correlates with the EM simulation data.
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页码：547 / 550
页数：4
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