Parallel decoding for burst error control codes

被引:7
|
作者
Fujiwara, E [1 ]
Namba, K
Kitakami, M
机构
[1] Tokyo Inst Technol, Grad Sch Informat Sci & Engn, Tokyo 1528552, Japan
[2] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1138656, Japan
关键词
burst error control codes; parallel decoding; nonsingular matrix; frames; byte error control codes;
D O I
10.1002/ecjc.10094
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is well known that sequential decoding methods for burst error control codes use Linear Feedback Shift Registers (LFSR). However, a parallel decoding method employing only combinational logic is preferable in certain applications, such as semiconductor memory systems and holographic memory systems, where a huge amount of data needs to be read or written at ultrahigh speed. This paper proposes a parallel decoding method for linear burst error control codes including the Fire code. In order to obtain the error pattern, this decoding method uses an inverse matrix of a nonsingular matrix which includes a sub-matrix of the parity check matrix. Burst error correction is possible because correct burst error patterns are obtained only from frames that completely include the burst error pattern. Furthermore, this decoding method can also be.. applied to single byte error correcting codes with less hardware. The implementation of decoding circuits for burst and byte error control codes are illustrated in this paper. And their hardware complexity is also evaluated to show that the proposed method requires less hardware than the existing parallel decoding method. Finally, we will discuss about how the proposed decoding method can be extended to correct multiple burst or byte errors. (C) 2003 Wiley Periodicals, Inc.
引用
收藏
页码:38 / 48
页数:11
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