Design of enhancement current-balanced logic for mixed, signal ICs

被引：0

作者：

Yang, L ^{[1
]}

Yuan, JS ^{[1
]}

机构：

[1] Univ Cent Florida, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The dual-V-T and negative feedback mechanisms have been proposed to enhance Current Balanced Logic for low noise IC design. The detailed circuit analysis and SPICE simulations show that the dual-VT structure has advantages over the conventional CBL design in many design aspects, such as gate area, delay, power dissipation, and switching noise. The negative feedback can further reduce the current spike with some tradeoffs. The design procedures of the enhancement CBL are discussed in detail. The proposed methods give the designer a better control of the current spike for mixed-signal integrated circuits.

引用

页码：761 / 764

页数：4

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