Using system-level timing analysis for the evaluation and synthesis of automotive architectures

被引:0
|
作者
Di Natale, Marco [1 ]
Zheng, Wei [2 ]
Giusto, Paolo [1 ]
机构
[1] Gen Motors Res & Dev, 30500 Mound Rd, Warren, MI 48090 USA
[2] Univ Calif Berkeley, Dept EECS, Berkeley, CA 94720 USA
关键词
automotive systems; real-time computing; timing analysis; schedulability;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Emerging technologies allow the implementation of advanced car features enhancing the safety and the comfort of the driver. These complex functions are distributed among several ECUs, implemented by multiple tasks executed on each processor, and are characterized by non-functional requirements, including timing constraints. The design of the physical architecture and the placement of tasks and messages must be performed in accordance with the constraints and optimizing the performance of the functions. We show how schedulability analysis can be used in the development of complex automotive systems to find the architectures that can best support the target application in a what-if iterative process, and we address the opportunities for the synthesis of architecture configurations. A case study of an experimental vehicle shows the applicability of the approach.
引用
收藏
页码:99 / +
页数:2
相关论文
共 50 条
  • [1] System-level analysis of fault effects in an automotive environment
    Corno, F
    Tosato, S
    Gabrielli, P
    [J]. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 529 - 536
  • [2] System-level Timing Feasibility Test for Cyber-physical Automotive Systems
    Tobuschat, Sebastian
    Ernst, Rolf
    Hamann, Arne
    Ziegenbein, Dirk
    [J]. 2016 11TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES), 2016,
  • [3] Transformation of SDL specifications for system-level timing analysis
    Jersak, M
    Richter, K
    Henia, R
    Ernst, R
    Slomka, F
    [J]. CODES 2002: PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2002, : 121 - 126
  • [4] Diversely Enumerating System-Level Architectures
    Jackson, Ethan K.
    Simko, Gabor
    Sztipanovits, Janos
    [J]. 2013 PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE (EMSOFT), 2013,
  • [5] Power analysis of system-level on-chip communication architectures
    Lahiri, K
    Raghunathan, A
    [J]. INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 236 - 241
  • [6] Evaluation of Architectures for an ASP MPEG-4 decoder using a system-level design methodology
    García, L
    Reyes, V
    Barreto, D
    Marrero, G
    Bautista, T
    Núñez, A
    [J]. VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2, 2005, 5837 : 785 - 794
  • [7] TIMING VERIFICATION FOR SYSTEM-LEVEL DESIGNS
    CHIANG, M
    BLOOM, M
    [J]. VLSI SYSTEMS DESIGN, 1987, 8 (13): : 46 - +
  • [8] Timing issues in system-level design
    Dasdan, A
    Gupta, RK
    [J]. IEEE COMPUTER SOCIETY WORKSHOP ON VLSI '98 - SYSTEM LEVEL DESIGN, PROCEEDINGS, 1998, : 124 - 129
  • [9] Early Timing Estimation for System-Level Design Using FPGAs
    Andrade, Hugo
    Ghosal, Arkadeb
    Limaye, Rhishikesh
    Malik, Sadia
    Petersen, Newton
    Ravindran, Kaushik
    Trung Tran
    Wang, Guoqiang
    Yang, Guang
    [J]. FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2012, : 271 - 271
  • [10] Global critical path: A tool for system-level timing analysis
    Venkataramani, Girish
    Budiu, Mihai
    Chelcea, Tiberiu
    Goldstein, Seth C.
    [J]. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2007, : 783 - +