Embedded systems design and verification: Reuse oriented prototyping methodologies

The SIA roadmap plans for 50 millions transistors asics/SOC in 2008 [1]. The design of these chips cannot be achieved in the required Time-to-Marker constraints without new methodologies. The key solution for saving design time is Design Reuse. However, while design reuse solves many design problems, it causes increased verification problems. The complexity of these new designs leads to simulation times that become prohibitive with regard to market pressure. The verification is thus achieved through high-speed emulation and prototyping technologies. The scope of this paper is to present these new methodologies. SPW [2] (from Cadence) can handle a wide variety of models in a cosimulation for virtual prototyping. Designs are verified by real prototyping on an Aptix reconfigurable platform, using DSP and FPGA components.