Limits to performance spread tuning using adaptive voltage and body biasing

被引：6
|
作者：
Meijer, M [1 ]
Pessolano, F [1 ]
de Gyvez, JP [1 ]
机构：
[1] Philips Res Labs, NL-5600 JA Eindhoven, Netherlands
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/ISCAS.2005.1464510
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (A-BB) design techniques. To serve this purpose, a test circuit was fabricated in a 90nm triple-well low-power CMOS technology. The analysis hereby presented is based on a ring oscillator running at 488MHz and a circular shift register with 8K flip-flops and 50K gates. Measurement results indicate that it is possible to reach 24.4x power savings by 6.1x frequency downscaling using AVS, +/- 24% power and +/- 22% frequency tuning at nominal conditions using A-BB only, 127x power savings with 37.4x frequency downscaling by combining AVS and ABB.
引用
收藏
页码：5 / 8
页数：4
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