Efficient Receiver Architecture for LDPC Coded BICM-ID System

被引：12
|
作者：
Cheng, Tao [1 ]
Peng, Kewu
Liu, Zaishuang
Yang, Zhixing
机构：
[1] Tsinghua Univ, Tsinghua Natl Lab Informat Sci & Technol, Res Inst Informat Technol, Beijing 100084, Peoples R China
来源：
IEEE COMMUNICATIONS LETTERS | 2015年 / 19卷 / 07期
基金：
中国国家自然科学基金;
关键词：
LDPC; BICM-ID; 3-D EXIT; full-parallel architecture; MODULATION;
D O I：
10.1109/LCOMM.2015.2426694
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
The low-density parity-check (LDPC) coded bit-interleaved coded modulation with iterative demapping (BICM-ID) has excellent bit error rate (BER) performance, but with extremely high receiver complexity. This letter proposes a three-stage full-parallel receiver architecture in which each component decoder is separately but simultaneously iteratively decoded. This architecture can make full use of the computing resources and improve the system performance without sacrificing the throughput. Three-dimensional (3-D) extrinsic information transfer (EXIT) analysis and BER simulations are carried out to demonstrate the superiority of the proposed new receiver architecture.
引用
收藏
页码：1089 / 1092
页数：4
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