Hardware synthesis for reconfigurable heterogeneous pipelined accelerators

This paper discusses a method of hardware synthesis for re-configurable heterogeneous pipelined accelerators and corresponding EDA-tool that we developed To evaluate the method and tool, we performed experiments using several representative image and signal processing cases. The experiments showed that our tool is able to automatically construct an optimized hardware that favorably compares to the hardware constructed by skilled human designers, but the tool does it several orders of magnitude faster than a human designer.