The use of Petri nets for the design and verification of asynchronous circuits and systems

被引:5
|
作者
Kondratyev, A [1 ]
Kishinevsky, M
Taubin, A
Cortadella, J
Lavagno, L
机构
[1] Univ Aizu, Aizu Wakamatsu 96580, Japan
[2] Univ Politecn Cataluna, Barcelona, Spain
[3] Politecn Torino, I-10129 Turin, Italy
关键词
D O I
10.1142/S0218126698000055
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Petri nets(46,37,45,48) are a powerful formalism for modeling concurrent systems. They are capable of implicitly describing a vast state space by a succinct representation which gracefully captures the notions of causality, concurrency and conflict between events. Petri nets have also been chosen by many authors as a formalism to describe the behavior of asynchronous circuits by interpreting the events as signal transitions, thus coining the term Signal Transition Graph (STG).(50,4) A design framework for asynchronous systems involves three main aspects: formal specification, verification and synthesis. In this paper we review the main techniques we have used to cover these aspects in recent years, with a special focus on asynchronous circuits.
引用
收藏
页码:67 / 118
页数:52
相关论文
共 50 条
  • [1] Automated verification of asynchronous circuits using circuit Petri nets
    Poliakov, Ivan
    Mokhov, Andrey
    Rafiev, Ashur
    Sokolov, Danil
    Yakovlev, Alex
    ASYNC 2008: 14TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2008, : 161 - 170
  • [2] Design and verification of pipelined circuits with Timed Petri Nets
    Parrot, Remi
    Briday, Mikael
    Roux, Olivier H. H.
    DISCRETE EVENT DYNAMIC SYSTEMS-THEORY AND APPLICATIONS, 2023, 33 (01): : 1 - 24
  • [3] Design and verification of pipelined circuits with Timed Petri Nets
    Rémi Parrot
    Mikaël Briday
    Olivier H. Roux
    Discrete Event Dynamic Systems, 2023, 33 : 1 - 24
  • [4] Verification of asynchronous circuits by BDD-based model checking of Petri nets
    Roig, O
    Cortadella, J
    Pastor, E
    APPLICATION AND THEORY OF PETRI NETS 1995, 1995, 935 : 374 - 391
  • [5] Timed Petri nets: Efficiency of asynchronous systems
    Bihler, E
    Vogler, W
    FORMAL METHODS FOR THE DESIGN OF REAL-TIME SYSTEMS, 2004, 3185 : 25 - 58
  • [6] Testable design verification using Petri nets
    Ruzicka, R
    EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2003, : 304 - 311
  • [7] Verification of asynchronous circuits using Time Petri Net unfolding
    Semenov, A
    Yakovlev, A
    33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 59 - 62
  • [8] Hardware and Petri nets: Application to asynchronous circuit design
    Cortadella, J
    Kishinevsky, M
    Kondratyev, A
    Lavagno, L
    Yakovlev, A
    APPLICATION AND THEORY OF PETRI NETS 2000, PROCEEDINGS, 2000, 1825 : 1 - 15
  • [9] Modelling, analysis and synthesis of asynchronous control circuits using Petri nets
    Yakovlev, AV
    Koelmans, AM
    Semenov, A
    Kinniment, DJ
    INTEGRATION-THE VLSI JOURNAL, 1996, 21 (03) : 143 - 170
  • [10] Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits
    Pena, MA
    Cortadella, J
    SECOND INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1996, : 222 - 232