A GATE LEAKAGE MODEL FOR DOUBLE GATE TUNNELING FIELD-EFFECT TRANSISTORS

被引：0

作者：

Zhu, Ying ^{[1
]}

Zhang, Lining ^{[1
]}

Zhang, Aixi ^{[1
]}

Chan, Mansun ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Kowloon, Hong Kong, Peoples R China

来源：

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2014年

关键词：

OXIDE;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Thinner gate dielectric favors larger drivability of TFETs but also leads to larger gate leakage. In this work, an analytical model is presented to capture the gate leakage current in double gate tunneling FET with ultrathin oxide thicknesses. Its accuracy is verified by TCAD simulations. This gate leakage module has been integrated with our previous TFET model e-TuT and its implications on TFET-based inverters are presented.

引用

页数：3

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