Integration of a long pulse laser thermal process for ultra shallow junction formation of CMOS devices

We present results on ultra-shallow junction formation for the sub 65 nm CMOS node by means of a Long Pulse Laser Thermal Process (LP-LTP). This method achieve to form abrupt and ultra-shallow junctions with low resistivities, but the different irradiated structures like transistor gates need to be preserved. To assess the integration of the laser process in the fabrication of a CMOS device, we studied the influence of optical coatings deposited before the laser irradiation in order to protect the structures. Different materials and coating thicknesses have been evaluated on blanket implanted wafers under a long pulse Excimer laser (200ns-15 J) irradiation. The junctions have been characterized by 4-point probe, in-situ reflectivity, UV photometry and transmission electronic microscopy (TEM) pictures. Irradiations have also been performed on coated CMOS structures with 35 nm junctions to assess the integration of the process on a real structure. A selective etching scanning electronic microscope (SEM) view shows that a proper optical coating optimizes the coupling of the deposited laser energy and is promising for improving the integration of the laser activation process of future CMOS junctions.