System on Chip Design for Multi-Principle of Relay Protection in the FPGA

被引:0
|
作者
Hu, Pengfei [1 ]
Yuan, Yuxiang [1 ]
Qu, Zhijuan [1 ]
Jiang, Xueping [1 ]
机构
[1] State Grid Smart Grid Res Inst, Beijing, Peoples R China
关键词
relay protection; FPGA; digital signal processing; hardware protection algorithms; process scheduling;
D O I
10.4028/www.scientific.net/AMM.668-669.857
中图分类号
TH [机械、仪表工业];
学科分类号
0802 ;
摘要
To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.
引用
收藏
页码:857 / 861
页数:5
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