Low-latency multi-level mesh topology for NoCs

被引：0

作者：

Saneei, Mohsen ^{[1
]}

Afzali-Kusha, Ali ^{[1
]}

Navabi, Zainalabedin ^{[2
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nanoelect Ctr Excellence, Tehran, Iran

[2] Univ Tehran, Elect & Comp Engn Dept, Comp Aided Design Lab, Tehran, Iran

来源：

2006 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2007年

关键词：

network-on-chip; latency; topology; Multi-Level Mesh; routers;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we introduce a new topology for network on chips which is named Multi-Level Mesh topology. The Multi-Level Mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications. This architecture reduces the latency of 3x3, 5x5, and 7x7 2-level mesh architectures about 12.5%, 21.4%, and 18.5% related to mesh architecture, respectively. The results are expected to improve further if a better adaptive routing algorithm is utilized.

引用

页码：36 / +

页数：2

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