A novel CMOS readout circuit for large format IRFPA with background current storage suppression

In this paper, we propose a novel readout circuit based on a buffered-direct-injection structure. In this new readout circuit, all the pixels in one row can start to integrate simultaneously. And the readout time can be reduced by as much as 94%. Since readout time in many conventional readout circuits contributes to half of the total row selection time, it is directly proportional to the total frame time. And the output waveform is boxcar, which is very easy to AD convert. In addition, one current storage cell is added into the readout circuit to achieve in-pixel background current suppression to remove the background component inherent in each pixel output. To increase the current mirror accuracy and the integration dynamic range, a cascode current mirror is also adopted in the readout circuit. SPICE simulation results have shown that the proposed readout circuit can achieve high charge sensitivity and resolution in a large format IRFPA with small pixel size.