A Load Balancing Scheme for Two-Stage Switches Maintaining Packet Sequence

被引:0
|
作者
Lee, Hyoung-Il [1 ]
Lee, Bhum-Cheol [2 ]
Seo, Seung-Woo [3 ]
机构
[1] Korean Intellectual Property Off, Elect & Elect Examinat Bur, Taejon 302701, South Korea
[2] ETRI, Broadband Convergence Network Res Div, Daejeon, 305350, South Korea
[3] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151, South Korea
关键词
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a novel load-balancing scheme for two-stage switches which does not disturb the sequence of packets. The proposed scheme uses chamber queues(CQs) in front of the second crossbar fabric as well as VOQs in front of the first crossbar. A chamber queue is composed of N banks each of which can store only one packet destined for each output. The two crossbar fabrics in the proposed switch are configured by a deterministic sequence of N connection patterns as in other two-stage switches. In a time slot, the proposed switch transfers packets from non-empty VOQs to the corresponding empty banks of CQs via the first crossbar, and the packets from CQs are switched to their destinations via the second crossbar. While the proposed scheme is very simple, it can achieve 100% throughput under not only uniform but also non-uniform traffic. Moreover, the simulation results show that the average delay of packets in the proposed two-stage switch is lower than that in the original two-stage switch.
引用
收藏
页码:293 / 298
页数:6
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