Effects of wafer bow and warpage on performance of electrostatic chucks in high volume manufacturing

被引:0
|
作者
Kurkowski, P [1 ]
Drizlikh, S [1 ]
Sarver, R [1 ]
Angis, H [1 ]
Loisel, P [1 ]
机构
[1] Natl Semicond Corp, Portland, ME 04106 USA
关键词
electrostatic chuck (ESQ; wafer warpage; wafer bow; BiCMOS;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper presents learnings authors gained when dealing with back side pressure faults (BSPF) on 200mm interconnect deposition tools equipped with minimum contact area (MCA) electrostatic chucks (ESC). It was found that BSPFs occurred more likely on chucks running mostly BiCMOS product. BiCMOS product was four times more susceptible to experience this fault than CMOS due to higher wafer bow and warpage which were traced to recrystallization of backside polysilicon at RTP emitter anneal. Moreover, a cost-effective rework scheme was implemented to prolong the life of ESC's. Long term solution of reducing wafer bow and warpage process is also being pursued.
引用
收藏
页码:128 / 130
页数:3
相关论文
共 50 条
  • [1] CDU Improvement with Wafer Warpage Control Oven for High Volume Manufacturing
    Tomita, T.
    Weichert, H.
    Hornig, S.
    Trepte, S.
    Shite, H.
    Uemura, R.
    Kitano, J.
    [J]. ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXVI, 2009, 7273
  • [2] ULTRA-HIGH-VACUUM COMPATIBLE WAFER TRANSPORT AND HOLDING SYSTEM USING ELECTROSTATIC CHUCKS
    OHMI, T
    ONODERA, M
    SATO, G
    SHIBATA, T
    MORITA, M
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1988, 135 (08) : C372 - C372
  • [3] THE ROAD TO WAFER-ON-WAFER (WOW) HIGH VOLUME MANUFACTURING (HVM)-ADVANCED SENSING IN WAFER HANDLING
    Kesil, Boris
    [J]. 2018 INTERNATIONAL WAFER LEVEL PACKAGING CONFERENCE (IWLPC), 2018,
  • [4] Progress in Nanoimprint Wafer and Mask Systems for High Volume Semiconductor Manufacturing
    Murasato, Naoki
    Arai, Tsuyoshi
    [J]. PHOTOMASK JAPAN 2018: XXV SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY, 2018, 10807
  • [5] Progress in Nanoimprint Wafer and Mask Systems for High Volume Semiconductor Manufacturing
    Imoto, Kohei
    Hiura, Mitsuru
    Morohoshi, Hiroshi
    Hayashi, Tatsuya
    Kimura, Atsushi
    Suzaki, Yoshio
    Choi, Jin
    [J]. PHOTOMASK TECHNOLOGY 2017, 2017, 10451
  • [6] THE FUTURE OF AUTOMATION FOR HIGH-VOLUME WAFER FABRICATION AND ASIC MANUFACTURING
    HUGHES, RA
    SHOTT, JD
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1987, 134 (8B) : C446 - C446
  • [7] THE FUTURE OF AUTOMATION FOR HIGH-VOLUME WAFER FABRICATION AND ASIC MANUFACTURING
    HUGHES, RA
    SHOTT, JD
    [J]. PROCEEDINGS OF THE IEEE, 1986, 74 (12) : 1775 - 1793
  • [8] Wafer level reliability application to manufacturing of high performance microprocessor
    Sarma, K
    Bahrami, M
    Mistry, K
    [J]. 1996 INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 1996, : 77 - 81
  • [9] Nanoimprint Wafer and Mask Tool Progress and Status for High Volume Semiconductor Manufacturing
    Matsuoka, Yoichi
    Seki, Junichi
    Nakayama, Takahiro
    Nakagawa, Kazuki
    Azuma, Hisanobu
    Yamamoto, Kiyohito
    Sato, Chiaki
    Sakai, Fumio
    Takabayashi, Yukio
    Aghili, Ali
    Mizuno, Makoto
    Choi, Jin
    Jones, Chris E.
    [J]. PHOTOMASK TECHNOLOGY 2016, 2016, 9985
  • [10] Effects of epitaxial silicon technology on the manufacturing performance of wafer fabrication lines
    Hughes, JC
    Neudeck, GW
    Uzsoy, R
    [J]. TWENTY THIRD IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 1998, : 333 - 336